1534291610432-s3_datasheet_v1.0.pdf (13.4 MB)
更多信息，可以看这里： http://www.sochip.com.cn/s3/index.php?title=What_is_S3_%3F
基本可以认为是在V3的基础上增加了128MByte SIP DDR3内存版本，非常像。
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S3 is a high cost-effective video encoding processor jointly developed by Zhuhai Allwinner Technology Co., Ltd. (“Allwinner”) and Sochip Technology Co., Ltd. (“Sochip”).
Its built-in single-core ARM Cortex-A7 runs at 1.2GHz with 1Gbit DRAM (DDR3) , supporting numerous peripheral devices. The Chip package is 234 balls FBGA package, size 11mm x 11mm , suitable for various types of product development.
Features
CPU
ARM Cortex A7 @ 1.2GHz
Support NEON Advanced SIMD instruction
VFPv4 Floating Point Unit
Video Encoding
Support H.264 video encoding profile BP/MP/HP
Support MJPEG/JPEG encoding
H.264 video encoding up to HD@120FPS/ FHD@60FPS
Support 4 ROI
Video Input
Support 8/10/12-bit CMOS sensor parallel interface
Support MIPI-CSI2 interface compliant with MIPI-DPHY v1.0 and MIPI-CSI2 v1.0
Support MIPI-CSI2 1/2/3/4 data lanes configuration
Support BT.656/ BT.1120
Image Processing
Support image mirror flip and rotation
Support two output channels
Speed up to 8MPixels@24fps
Defect pixel correction
Super lens shading correction
Anisotropic non-linear Bayer interpolation with false color suppression
Programmable color correction
Advanced contrast enhance and sharping
Advanced saturation adjust
Advanced spatial(2D) de-noise filter
Advanced chrominance noise reduction
Zone-based AE/AF/AWB statistics
Anti-flick detection statistics
Histogram statistics
Video output
Support LVDS interface with single link, up to 1024x768@60fps
Support RGB interface with DE/SYNC mode, up to 1024x768@60fps
Support serial RGB/dummy RGB/CCIR656 interface, up to 800x480@60fps
Support i80 interface with 18/16/9/8 bit, support TE, up to 800x480@60fps
Audio Interface
Integrate Audio Codec
Support I2S/PCM interface
External Storage
Support SPI Nor Flash
Support SPI Nand Flash
Support SD/TF card
Support eMMC
Peripheral Interface
One USB 2.0 OTG controller with PHY
Support RGMII/MII/RMII interface. Integrated an internal 10/100M PHY
Up to three UART controllers
Up to two Two Wire Interface(TWI)controllers
Security Engine
Support AES, DES, 3DES, SHA-1, MD5
Package
FBGA 234 balls
0.65mm ball pitch, 11mm x 11mm