EPHY-25M clock issue


My project based on MangoPi MQ (D1S / F133). Used eternet PHY on RMII interface,
need 25 MHz external clock.

I’m builded own system image on MangoPi SDK/Buildroot. To use eternet PHY, i’m modify
device tree:

  • changed necessary GPIO pins
  • changed “phy-mode” to “rmii” from “rgmii” at gmac0 node.

No more changes.

When system loaded and interface eth0 is up, EPHY-25M clock signal is absent.
It is because special clocks in CCU register “EMAC_25M_CLK_REG” (0x0970) are gated.

How to fix it?
Some missing in device tree? Or in kernel driver?

I’made user-space test program, which enable clock in EMAC_25M_CLK register, and all work.